• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a deformatting apparatus for digital VRLs, and more particularly, to a deformatting apparatus for digital VRLs to be stored together in an AC data memory without separately storing DC data. Since there is no need to configure a separate address for controlling the DC memory has the effect of making the process of the signal faster and easier.
    公开号:KR19990032108A
    申请号:KR1019970053077
    申请日:1997-10-16
    公开日:1999-05-06
    发明作者:김인철
    申请人:전주범；대우전자 주식회사；
    IPC主号:
    专利说明:

    DEFORMATTING APPARATUS FOR A DIGITAL VCR
    BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a deformatting apparatus for digital BCs, and more particularly, to a deformatting apparatus for digital BCs to be stored together in an AC data memory without separately storing DC data.
    1 is a block diagram illustrating a conventional general digital de-formatting apparatus.
    As shown in FIG. 1, the conventional deformatting apparatus of digital VRs uses QNO, STA, DC, AC to input data input in 8-bit units from an error correction code (ECC) processor. A split unit 100 classified into components and stored in each memory, and AC data among ECC data of one segment unit classified from the split unit 100 is stored in DCT block and macro block units by a ping-pong structure. The address of the AC data is generated when the first memory 110 and the second memory 111 and the AC data output from the split unit 100 are stored in the first memory 110 and the second memory 111. The AC address generator 112, the DC memory 120 storing QNO and DC data among the ECC data classified from the split unit 100, and the QNO and DC data output from the split unit 100. When stored in the DC memory 120 The DC address generation unit 121 for generating an address of the existing data, and AC data of one segment unit stored in the first memory 110 and the second memory 111 are packed in units of 16 bits, and the 16 bit data. Decoder 130 to generate Run and Amplitude, which are the number of consecutive zeros, and store them in DCT block units, and Run, Amp values decoded and output from the deformatter 130 by DCT by a ping-pong structure. The third memory 140 and the fourth memory 141 stored in block units, and the run and amp values output from the deformatter 130 are stored in the third memory 140 and the fourth memory 141. When the address of the data is generated by the RA address generator 142.
    The deformatting process of the conventional general digital VR configured as described above will be described in detail.
    First, ECC data of one segment unit, which is formatted and input from an ECC processing unit, is classified into QNO, STA, DC, and AC components by the split unit 100 and stored in each memory, and the AC component data is stored in one segment unit. The first memory 110 and the second memory 111 having the ping-pong structure are stored, and the data of the QNO and DC components are stored in the DC memory 120 in two consecutive segments.
    At this time, when storing the AC and DC data in each memory, each address generator 112, 121 generates and stores its address, wherein the generated address bits are the AC address according to the number of words of data to be processed. Is 8 bits, and the DC address is 6 bits.
    2 illustrates the structure of ECC data in units of one segment.
    As shown in FIG. 2, ECC data in units of one segment is composed of five macro blocks MB1, MB2, MB3, MB4, and MB5, and each macro block includes a quantization number (QNO) consisting of one byte and It consists of error correction information (STA), four Y DCT blocks (DCT1, DCT2, DCT3, and DCT4) each of 14 bytes, a Cr DCT block (DCT5) consisting of 10 bytes each, and a Cb DCT block (DCT6). .
    Thus, one macroblock totals 77 bytes (1 byte + 14 bytes) × 4 DCT + 10 bytes × 2 DCT), and ECC data in one segment unit totals 385 bytes (77 bytes). × 5 MB).
    Here, the QNO and DCI portions of FIG. 2 are stored in the DC memory 120. The QNO consists of 4 bits, and the DCI consists of a 9-bit DC coefficient, a 1-bit mode, and a 2-bit class number. When 16 bits, or 1 word, are stored per DCT block, and calculated as ECC data in units of 1 segment, a total of 30 words (1 word) × 30 DCT), the DC memory 120 stores two segments of DC data, that is, 60 words of data.
    Therefore, when storing the 60 words of DC data in the DC memory 120, the DC address generator 121 has 6 bits (the minimum number of address bits for processing m words is m = 2 k Must be configured to address).
    In addition, in the DCT1 to DCT4 including 14 bytes (112 bits) of the ECC data of one segment unit, 100 bits of AC data exist except for 12 bits of DC data. 100 ÷ The DCT5 and DCT6, which are processed in 16) and consist of 10 bytes (80 bits), have 68 bits of AC data except for 12 bits of DC data, which is 5 words (68). ÷ 16).
    Therefore, if you calculate this in 1-segment units, a total of 190 words (7 words × 20 DCT + 5 words × Since AC data of 10 DCT) must be processed, the AC address generator 112 has 8-bit addresses in the first memory 110 and the second memory 111 whenever ECC data of one segment is input. Configure and save.
    QNO and DC data stored in the DC memory 120 among the data classified and stored in the above process are output as an inverse quantization block.
    The AC data stored in the first memory 110 and the second memory 111 is deformatted through the deformatter 130 and stored in the third memory 140 and the fourth memory 141. It will be described in detail.
    First, each ECC data classified by the split unit 100 has a ping-pong structure so that the classification and storage process is performed simultaneously with the deformatting operation.
    That is, when an Nth segment block is written to the first memory 110 and then started to be read by the deformatter 130, the second memory 111 receives and writes an N + 1th segment block. do.
    In addition, when the writing of the N + 1th segment block is completed in the second memory 111 and started to be read by the formatter 130, the first memory 110 applies the N + 2th segment block from the ECC. It will write it.
    In this manner, the AC data stored in the first memory 110 and the second memory 111 and input to the deformatter 130 is packed into 16 bits and decoded through pass 1, pass 2, and pass 3 processes. RUN and AMP values are generated.
    Here, the pass 1 process is to decode in units of DCT blocks, and decodes the RUN and AMP values of the corresponding block from the data in each DCT block. When decoding one DCT block, the end of block (EOB) is decoded. It will remember the address and bit position, and continue decoding the next DCT block.
    In addition, if the EOB cannot be decoded while decoding the block, it is a process of decoding 30 DCT blocks by memorizing the last address and bit that generated the RUN and AMP values in the block and continuing decoding the next DCT block in the same manner.
    Pass 2 is a process of decoding in macro block units (6 DCT blocks), which packs the valid bits remaining in the undecoded DCT block of the macro block and the next valid bit next to the EOB in the decoded DCT block. Are packed consecutively and decoded.
    If the EOB occurs during decoding, the address and location are memorized again. If the EOB does not occur, the next step is repeated by packing and decoding the bits following the EOB in the decoded DCT block.
    When an EOB occurs, if there is another DCT block in which the EOB has not been decoded in the macro block, the above process is repeatedly repeated.
    The pass 3 process is a process of decoding in segment units (30 DCT blocks, that is, 5 macro blocks). In a similar manner to the pass 2 process, the pass 3 process repacks and decodes valid bits that were not decoded in the pass 2 process. If no DCT exists, the process adds an EOB to the end of the DCT block.
    The generated order pair (RUN, AMP) values are applied to and stored in the third memory 140 and the fourth memory 141 having the ping-pong structure, and the final data value of each DCT block corresponds to the symbol EOB.
    In this case, the third memory 140 and the fourth memory 141 store data of a DCT block unit in which (RUN, AMP) values are generated. Since one DCT block AC data has a maximum size of 64 words, Up to 1920 words (64 words per segment data) × 30 DCT) is stored.
    Therefore, the RA address generator 142 configures and stores 11 bits of address bits when storing the (RUN, AMP) values in the third memory 140 and the fourth memory 141.
    The (RUN, AMP) values of the DCT block units stored in the third memory 140 and the fourth memory 141 are output to the inverse quantization block to perform inverse quantization.
    However, by classifying and storing the AC and DC data in the de-formatting process performed as described above, an address for controlling each memory must be separately configured, which causes a complicated process.
    In order to improve such a problem, an object of the present invention is to provide a de-formatting device of digital VR to store the DC data together in the AC data memory without storing them separately.
    Means for achieving the above object is a split unit for classifying the data input from the ECC processing unit into QNO, STA, DC, AC components and storing them in the memory, QNO of ECC data of one segment unit classified from the split unit, First and second memories in which DC and AC data are stored in DCT block and macro block units by a ping-pong structure, and when storing the AC and DC data in the first and second memories, an address of the data is generated. An AD address generator, a deformatter for packing AC data among the data stored in the first and second memories in 16 bit units, decoding the 16 bit data into Run and Amplitude values, and storing the AC data in units of DCT blocks; (Run, Amp) values of AC data decoded and output by the deformatter, and third and fourth memories in which DC data are stored in DCT block units by a ping-pong structure; (Run, Amp) value of the AC data output from the deformatter, and RA address generation unit for generating the address of the data when storing the DC data in the third and fourth memory characterized in that it comprises a.
    1 is a block diagram showing a deformatting apparatus of a general digital VR.
    2 is a diagram showing a configuration of one segment of formatted ECC data.
    3 is a block diagram showing a deformatting apparatus of a digital VR according to an embodiment of the present invention.
    <Explanation of symbols for main parts of the drawings>
    200: split portion 210: first memory
    220: second memory 230: AD address generator
    240: deformatter 250: third memory
    260: fourth memory 270: RA address generator
    3 is a block diagram illustrating an apparatus for deformatting a digital VR according to an embodiment of the present invention.
    As shown in FIG. 3, the present invention divides data input from an ECC processing unit into QNO, STA, DC, and AC components, and stores them in a memory, respectively, and is divided from the split unit 200. The first memory 210 and the second memory 220 in which QNO, DC, and AC data of ECC data in one segment unit are stored in DCT block and macro block units by a ping-pong structure, and the AC and DC data are stored in the first memory 210. First, the AD address generator 230 generates an address of the data when the first memory 210 and 220 are stored in the first memory, and the AC data among the data stored in the first and second memories 210 and 220 is 16 bits. Packed in units, the deformatter 240 to decode the 16-bit data into Run and Amplitude values to be stored in units of DCT blocks, and the ordered pair (Run, Amp) of the AC data decoded by the deformatter 240 Value and DC data into the ping-pong structure The third memory 250 and the fourth memory 260 stored in the DCT block unit, and the (Run, Amp) value and the DC data of the AC data output from the deformatter 240 are the third, fourth RA address generator 270 for generating the address of the data when stored in the memory (250, 260).
    The operation process of the de-formatting apparatus of the digital VR according to the embodiment of the present invention configured as described above will be described in detail as follows.
    First, data that is formatted and input from an ECC processing unit is classified into QNO, STA, DC, and AC components by the split unit 200, and the QNO, DC, and AC data of ECC data in units of one segment are divided into first and second memories ( 210 and 220, which are stored in a ping-pong structure in order to simultaneously classify and store ECC data in units of one segment.
    That is, when the N-th segment block is written to the first memory 210 and then started to be read by the deformatter 240, the second memory 220 receives and writes the N + 1th segment block. do.
    In addition, when writing of the N + 1th segment block is completed in the second memory 220 and then being read by the formatter 240, the first memory 210 applies the N + 2th segment block from the ECC. It will write it.
    Here, when storing the ECC data of the one-segment unit in the first and second memories 210 and 220, an address controlling the memory is configured in the AD address generator 230. As mentioned, it depends on the number of words of data to be processed.
    Accordingly, the data of one segment block stored in the first and second memories 210 and 220 is 220 words in total, including 30 DC data and 190 AC data, as described above. It is sufficient to construct an address of 8 bits without the address bits to be made.
    Therefore, the process of separately configuring the 6-bit address is omitted by storing DC data separately.
    As described above, AC data among the data stored in the first memory 210 and the second memory 220 is applied to the formatter 240 and decoded by the processes of pass 1, pass 2, and pass 3 (RUN, AMP). After the value is generated, it is stored in the third memory 250 and the fourth memory 260 in units of DCT blocks, and the DC data is applied as it is, along with the generated (RUN, AMP) values. It is stored in the memory (250, 260).
    In this case, an address controlling the third memory 250 and the fourth memory 260 is generated by the RA address generator 270, and the data stored in the third and fourth memories 250 and 260 is AC. Since the (RUN, AMP) value 1920 words of the data and the 30 words of the DC data are added together, the total number is 1950 words. Thus, the RA address generation unit 270 only needs to configure an 11-bit address as in the prior art.
    In this way, the (RUN, AMP) values and DC data of the DCT block units stored in the third memory 250 and the fourth memory 260 are output to the inverse quantization block to perform inverse quantization operation.
    As described in detail above, the present invention saves the DC data together in the AC memory, and thus does not need to configure a separate address for controlling the DC memory, thereby making it possible to process the signal faster and easier. .
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] A split unit for classifying data from the ECC processing unit into QNO, STA, DC, and AC components and storing the data in a memory;
    First and second memories in which QNO, DC, and AC data of ECC data of one segment unit classified from the split unit are stored in DCT block and macro block units by a ping-pong structure;
    An AD address generator for generating an address of the data when storing the AC and DC data in the first and second memories;
    A deformatter configured to decode AC data among the data stored in the first and second memories to generate Run and Amplitude values and store the values in DCT block units;
    Third and fourth memories in which ordered pairs (Run, Amp) values of AC data decoded and output by the deformatter and DC data are stored in DCT block units by a ping-pong structure;
    And a RA address generator for generating an address of the data when storing the (Run, Amp) value of the AC data output from the deformatter and the DC data in the third and fourth memories. Deformatting device.
    [2" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the data stored in the first and second memories is 220 words each.
    [3" claim-type="Currently amended] The apparatus of claim 1, wherein the address generated by the AD address generator is 8 bits.
    [4" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the data stored in the third and fourth memories is 1950 words, respectively.
    [5" claim-type="Currently amended] The apparatus of claim 1, wherein the address generated by the RA address generator is 11 bits.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-16|Application filed by 전주범, 대우전자 주식회사
    1997-10-16|Priority to KR1019970053077A
    1999-05-06|Publication of KR19990032108A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970053077A|KR19990032108A|1997-10-16|1997-10-16|Digital V Deformatting Device|
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